Semiconductor devices having highly integrated sheet and wire patterns therein

ABSTRACT

A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

REFERENCE TO PRIORITY APPLICATION

This application claims priority under 35 U.S.C. 119 to Korean PatentApplication No. 10-2021-0075786, filed Jun. 11, 2021, the disclosure ofwhich is hereby incorporated herein by reference.

BACKGROUND

The present disclosure relates to semiconductor devices and, moreparticularly, to highly integrated semiconductor devices with verticallyintegrated components therein.

As one of many scaling technologies for increasing density of asemiconductor device, a multi gate transistor in which a fin ornanowire-shaped multi-channel active pattern (or a silicon body) isformed on a substrate and a gate is formed on a surface of themulti-channel active pattern, has been proposed. Since such a multi gatetransistor utilizes three-dimensional channels, scaling is relativelyeasily performed. Moreover, even if a gate length of the multi gatetransistor is not increased, the current control capability may beimproved. The SCE (short channel effect), in which potential of achannel region is influenced by a drain voltage, may also be effectivelysuppressed. Unfortunately, as a pitch size of a semiconductor devicedecreases, there is an increasing need for a research for securing adecrease in capacitance and electrical stability between contacts withinthe semiconductor device.

SUMMARY

Aspects of embodiments of the present invention provide semiconductordevices having improved device performance and reliability.

According to aspects of embodiments of the present invention, there isprovided a semiconductor device including a substrate (e.g.,semiconductor substrate) having first and second regions therein. Afirst lower semiconductor pattern is provided, which protrudes from thesubstrate (in the first region) and extends lengthwise in a firstdirection. A first gate electrode is provided, which extends in a seconddirection across the first lower semiconductor pattern. A plurality ofsheet patterns are provided, which are spaced apart, in a vertical stackof sheet patterns, from the first lower semiconductor pattern in a thirddirection, which is orthogonal to the first direction and to the seconddirection. A first gate insulating film is provided, which wraps aroundeach of the plurality of sheet patterns. A second lower semiconductorpattern is provided, which protrudes from the substrate (in the secondregion) and extends lengthwise in the first direction. A plurality ofwire patterns are provided, which are spaced apart in the thirddirection from the second lower semiconductor pattern. A second gateinsulating film is provided, which wraps around each of the wirepatterns. In these embodiments, a thickness of the first gate insulatingfilm is less than a thickness of the second gate insulating film, and adistance at which each of the sheet patterns is spaced in the thirddirection is smaller than a distance at which each of the wire patternsis spaced in the third direction.

According to another embodiment of the present invention, there isprovided a semiconductor device, which includes a first region and asecond region of a substrate, a first lower semiconductor pattern whichprotrudes from the substrate of the first region and extends in a firstdirection, a first gate electrode which extends in a second direction(orthogonal to the first direction) on the first lower semiconductorpattern, and a plurality of sheet patterns, which are spaced apart fromthe first lower semiconductor pattern in a third direction (orthogonalto the first and second directions). A first gate insulating film isprovided, which wraps around each of the plurality of sheet patterns.This first gate insulating film includes a first interface film, and afirst high dielectric constant film on the first interface film. Asecond lower semiconductor pattern is provided, which protrudes from thesubstrate (in the second region) and extends in the first direction. Asecond gate electrode is provided, which extends in the second directionon the second lower semiconductor pattern. A plurality of wire patternsare provided, which are spaced apart from the second lower semiconductorpattern in the third direction. A second gate insulating film isprovided, which wraps around each of the wire patterns. The second gateinsulating film includes a second interface film and a second highdielectric constant film on the second interface film. A thickness ofthe first interface film is less than a thickness of the secondinterface film, in some embodiments of the invention.

According to another embodiment of the invention, a semiconductor deviceis provided, which includes a substrate having at least first and secondregions therein. A first lower semiconductor pattern is provided, whichprotrudes from the first region and extends lengthwise in a firstdirection across the substrate. A first gate electrode is provided,which extends across the first lower semiconductor pattern in a seconddirection that is orthogonal to the first direction. First to thirdsheet patterns are provided, which are sequentially stacked on the firstlower semiconductor pattern in a third direction, which is orthogonal tothe first and second directions. A first gate insulating film isprovided, which wraps around the first to third sheet patterns. Thisfirst gate insulating film includes a first interface film, and a firsthigh dielectric constant film on the first interface film. A secondlower semiconductor pattern is provided, which protrudes from the secondregion and extends lengthwise across the substrate in the firstdirection. A second gate electrode is provided, which extends in thesecond direction on the second lower semiconductor pattern. First tothird wire patterns are provided, which are vertically stacked in thethird direction on the second lower semiconductor pattern. A second gateinsulating film is provided, which wraps around the first to third wirepatterns. The second gate insulating film includes a second interfacefilm and a second high dielectric constant film on the second interfacefilm. In addition, from a viewpoint of a cross-sectional area, the firstwire pattern includes a first surface extending in the second direction,and a second surface connected to both ends of the first surface (andhaving a concave curved surface with respect to the second lowerpattern). Likewise, from a viewpoint of the cross-sectional area, thesecond wire pattern includes a first sub-wire pattern, in which a widthin the second direction gradually increases as it gets farther from thesecond lower pattern, and a second sub-wire pattern, which is placed onthe first sub-wire pattern and has a width in the second direction thatgradually decreases as it gets farther from the second lower pattern. Aheight of the first sub-wire pattern in the third direction may besmaller than a height of the second sub-wire pattern in the thirddirection. And, from a viewpoint of the cross-sectional area, the thirdwire pattern may have an elliptical shape in which a width in the seconddirection is smaller than a width in the third direction.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and features of the present disclosure willbecome more apparent by describing in detail exemplary embodimentsthereof with reference to the attached drawings, in which:

FIG. 1 is an exemplary plan layout diagram of a semiconductor deviceaccording to some embodiments.

FIG. 2 is an exemplary cross-sectional view taken along lines A-A′ andB-B′ of FIG. 1 .

FIG. 3 is an exemplary cross-sectional view taken along lines C-C′ andD-D′ of FIG. 1 .

FIG. 4 is an enlarged view of region P and region Q of FIG. 2 .

FIG. 5 is an enlarged view of region R and region S of FIG. 3 .

FIG. 6 is an enlarged view of region T of FIG. 5 .

FIG. 7 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 8 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 9 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 10 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 11 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 12 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 13 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 14 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 15 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 16 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIG. 17 is a cross-sectional diagram of a semiconductor device accordingto some embodiments.

FIGS. 18 to 33 are cross-sectional views of intermediate structures thatillustrate methods of fabricating semiconductor devices according tosome embodiments of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Although the drawings of a semiconductor device described herein show afin-type transistor (FinFET) including a channel region of a fin-typepattern shape, a transistor including a nanowire or a nanosheet, and aMBCFET™ (Multi-Bridge Channel Field Effect Transistor) as an example,the embodiments are not limited thereto. For example, the semiconductordevice according to some embodiments may include a tunneling transistor(tunneling FET) or a three-dimensional (3D) transistor. Thesemiconductor device according to some embodiments may also include aplanar transistor. In addition, the many technical concepts described inthis specification may be applied to transistors based ontwo-dimensional materials (2D material based FETs) and heterostructuresthereof. Furthermore, semiconductor devices according to someembodiments may also include a bipolar junction transistor, a laterallydiffused metal oxide semiconductor (LDMOS), or the like.

FIG. 1 is an exemplary layout diagram for explaining a semiconductordevice according to some embodiments. FIG. 2 is an exemplarycross-sectional view taken along lines A-A′ and B-B′ of FIG. 1 , andFIG. 3 is an exemplary cross-sectional view taken along lines C-C′ andD-D′ of FIG. 1 . Referring to FIGS. 1 to 3 , the semiconductor deviceaccording to some embodiments may include a first substrate 100, asecond substrate 200, a first gate electrode 120, a second gateelectrode 220, a first active contact CA1, a second active contact CA2,a first gate contact 160, and a second gate contact 260. The firstsubstrate 100 may be formed in a first region I. The second substrate200 may be formed in a second region II. The first region I and thesecond region II may be, but are not limited to, regions adjacent toeach other and may be regions spaced apart from each other.

In some embodiments, the first region I may be, for example, a region inwhich a first drive voltage transistor is formed. The second region IImay be, for example, a region in which a second drive voltage transistoris formed. The first drive voltage may be lower than the second drivevoltage. For example, the first transistor may be a transistor used fora low voltage. The second transistor may be a transistor used for a highvoltage.

The first substrate 100 may include a first active region RX1. Thesecond substrate 200 may include a second active region RX2. Althoughnot shown, a first field region may be formed on both sides of the firstactive region RX1 to be directly adjacent to the first active regionRX1. Similarly, a second field region may be formed on both sides of thesecond active region RX2 to be directly adjacent to the second activeregion RX2. The first active region RX1 may be separated by the firstfield region. The second active region RX2 may be separated by thesecond field region.

Explained by another method, an element isolation film may be placedaround the first active region RX1. At this time, a portion of theelement isolation film between the first active regions RX1 spaced apartfrom each other may be the first field region. The element isolationfilm may be placed around the second active region RX2. At this time, aportion of the element isolation film between the second active regionsRX2 spaced apart from each other may be the second field region.

For example, a portion in which a channel region of the transistor isformed may be the active region, and a portion that divides the channelregion of the transistor formed in the active region may be the fieldregion. Alternatively, the active region may be a portion in which ananosheet or a nanowire used as the channel region of the transistor isformed, and the field region may be a region in which the nanosheet ornanowire used as the channel region is not formed.

In some embodiments, one of the first active region RX1 or the secondactive region RX2 may be a PMOS formation region and the other may be anNMOS formation region. In another embodiment, the first active regionRX1 and the second active region RX2 may be the PMOS formation region.In another embodiment, the first active region RX1 and the second activeregion RX2 may be the NMOS formation region.

The first substrate 100 and the second substrate 200 may be a siliconsubstrate or a SOI (silicon-on-insulator) substrate, for example. Incontrast, the substrate 100 may include, but is not limited to, silicongermanium, SGOI (silicon germanium on insulator), indium antimonide,lead tellurium compounds, indium arsenic, indium phosphide, galliumarsenide or gallium antimonide.

A first lower pattern BP1 may be formed on the first active region RX1.The first lower pattern BP1 may protrude from the first substrate 100.The first lower pattern BP1 may extend long along a first direction X onthe first substrate 100. For example, the first lower pattern BP1 mayinclude a long side extending in the first direction X, and a short sideextending in a second direction Y. Here, the first direction X mayintersect the second direction Y and a third direction Z. Also, thesecond direction Y may intersect the third direction Z. A second lowerpattern BP2 may be formed in the second active region RX2. The secondlower pattern BP2 may protrude from the second substrate 200. The secondlower pattern BP2 may extend long along the first direction X on thesecond substrate 200. For example, the second lower pattern BP2 mayinclude a long side extending in the first direction X, and a short sideextending in the second direction Y.

In some embodiments, a plurality of sheet patterns SP may be included onthe first lower pattern BP1. Although the three sheet patterns SP areshown, this is only for convenience of explanation, and the embodimentsdescribed herein are not limited thereto.

The plurality of sheet patterns SP may include a first sheet patternSP1, a second sheet pattern SP2, and a third sheet pattern SP3. Thefirst sheet pattern SP1, the second sheet pattern SP2, and the thirdsheet pattern SP3 may be sequentially placed on the first lower patternBP1. The first sheet pattern SP1, the second sheet pattern SP2, and thethird sheet pattern SP3 may be spaced apart from each other in the thirddirection Z (in a vertical stack). The first sheet pattern SP1 may belocated between the second sheet pattern SP2 and the first lower patternBP1. The second sheet pattern SP2 may be located between the third sheetpattern SP3 and the first sheet pattern SP1. The sheet pattern SP maypenetrate the first gate electrode 120 and be connected to a firstsource/drain pattern 170. The sheet pattern SP may be a channel patternwhich is used as a channel region of a transistor. For example, thesheet pattern SP may be a nanosheet.

A plurality of wire patterns WP may be included on the second lowerpattern BP2. Although the three wire patterns WP are shown, this is onlyfor convenience of explanation, and the embodiment is not limitedthereto. The plurality of wire patterns WP may include a first wirepattern WP1, a second wire pattern WP2, and a third wire pattern WP3.The first wire pattern WP1, the second wire pattern WP2, and the thirdwire pattern WP3 may be sequentially placed on the second lower patternBP2. The first wire pattern WP1, the second wire pattern WP2, and thethird wire pattern WP3 may be spaced apart from each other in the thirddirection Z. The first wire pattern WP1 may be located between thesecond wire pattern WP2 and the first lower pattern BP2. The second wirepattern WP2 may be located between the third wire pattern WP3 and thefirst wire pattern WP1.

The wire pattern WP may penetrate the second gate electrode 220, and beconnected to the second source/drain pattern 270. The wire pattern WPmay be a channel pattern which is used as the channel region of thetransistor. For example, the wire pattern WP may be a nanowire.

The first lower pattern BP1 and the sheet pattern SP may each be a partof the first substrate 100, and may include an epitaxial layer that isgrown from the first substrate 100. The second lower pattern BP2 and thewire pattern WP may each be a part of the second substrate 200, and mayinclude an epitaxial layer that is grown from the second substrate 200.

The first lower pattern BP1, the sheet pattern SP, the second lowerpattern BP2, and the wire pattern WP may include, for example, siliconor germanium, which are elemental semiconductor materials. Further, thefirst lower pattern BP1, the sheet pattern SP, the second lower patternBP2, and the wire pattern WP may include a compound semiconductor, andmay include, for example, a group IV-IV compound semiconductor or agroup III-V compound semiconductor.

The group IV-IV compound semiconductor may include, for example, abinary compound or a ternary compound including at least two or more ofcarbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compoundobtained by doping these elements with a group IV element. The groupIII-V compound semiconductor may be, for example, at least one of abinary compound, a ternary compound or a quaternary compound formed bycombining at least one of aluminum (Al), gallium (Ga) and indium (In) asa group III element with one of phosphorus (P), arsenic (As) andantimony (Sb) as a group V element.

A first field insulating film 105 may be formed on the first substrate100. At least a part of the first field insulating film 105 may beformed over the first active region RX1. In addition, the first fieldinsulating film 105 may be formed on a part of a side wall BP1_SW of thefirst lower pattern BP1. The first lower pattern BP1 may protrude upwardfrom the upper surface of the first field insulating film 105. That is,an upper surface BP1_US of the first lower pattern BP1 may be formed tobe higher than the upper surface of the first field insulating film 105,as illustrated.

A second field insulating film 205 may be formed on the second substrate200. At least a part of the second field insulating film 205 may beformed over the second active region RX2. The second field insulatingfilm 205 may be formed on a part of a side wall BP2_SW of the secondlower pattern BP2. The second lower pattern BP2 may protrude upward fromthe upper surface of the second field insulating film 205. That is, anupper surface BP2_US of the second lower pattern BP2 may be formed to behigher than the upper surface of the second field insulating film 205,as illustrated.

The first field insulating film 105 and the second field insulating film205 may include, for example, an oxide film, a nitride film, anoxynitride film or a combination film thereof. The first gate structureGS1 may be placed on the first lower pattern BP1. The second gatestructure GS2 may be placed on the second lower pattern BP2. The firstgate structure GS1 may intersect the first lower pattern BP1. The secondgate structure GS2 may intersect the second lower pattern BP2.

The first gate structure GS1 may include, for example, a first gateelectrode 120, a first gate insulating film 130, a first gate spacer140, and a first gate capping pattern 150. The second gate structure GS2may include, for example, a second gate electrode 220, a second gateinsulating film 230, a second gate spacer 240, and a second gate cappingpattern 250. The first gate electrode 120 may be formed on the firstlower pattern BP1. The first gate electrode 120 may intersect the firstlower pattern BP1. The first gate electrode 120 may include a long sideextending in the second direction Y, and a short side extending in thefirst direction X.

An upper surface of the first gate electrode 120 may be, but is notlimited to, a concave curved surface that is recessed toward the firstlower pattern BP1. Unlike the shown example, the upper surface of thefirst gate electrode 120 may be a flat plane. The second gate electrode220 may be formed on the second lower pattern BP2. The second gateelectrode 220 may intersect the second lower pattern BP2. The secondgate electrode 220 may include a long side extending in the seconddirection Y, and a short side extending in the first direction X. Anupper surface of the second gate electrode 220 may be, but is notlimited to, a concave curved surface that is recessed toward the secondlower pattern BP2. Unlike the shown example, the upper surface of thesecond gate electrode 220 may be a flat plane.

In some embodiments, a volume (and cross-sectional area) of the firstgate electrode 120 may be greater than a volume (and cross-sectionalarea) of the second gate electrode 220. From the viewpoint of across-sectional area, a cross-sectional area of the first gate electrode120 may be greater than a cross-sectional area of the second gateelectrode 220. Because the thickness of the first gate insulating film130 is thinner than the thickness of the second gate insulating film230, the volume of the first gate electrode 120 may be greater than thevolume of the second gate electrode 220.

Each of the first gate electrode 120 and the second gate electrode 220may include, for example, at least one of titanium nitride (TiN),tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride(TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride(TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride(TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum(TiAl), titanium aluminum carbonitride (TiAlC—N), titanium aluminumcarbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN),tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti),tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt),niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum(Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungstencarbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os),silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinationsthereof.

Each of the first gate electrode 120 and the second gate electrode 220may include a conductive metal oxide, a conductive metal oxynitride, andthe like, and may also include an oxidized form of the above-mentionedmaterials. The first gate spacer 140 may be placed on the side wall ofthe first gate electrode 120. The first gate spacer 140 may extend inthe second direction Y. The second gate spacer 240 may be placed on theside wall of the second gate electrode 220. The second gate spacer 240may extend in the second direction Y.

Each of the first gate spacer 140 and the second gate spacer 240 mayinclude, for example, at least one of silicon nitride (SiN), siliconoxynitride (SiON), silicon oxide (SiO₂), silicon oxycarbonitride(SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN),silicon oxycarbide (SiOC), and combinations thereof. The first gateinsulating film 130 may extend along the side wall and bottom surface ofthe first gate electrode 120. The first gate insulating film 130 maywrap around the sheet pattern SP. The first gate insulating film 130 mayinclude a first interface film 131 and a first high dielectric constantfilm 132.

The first interface film 131 may be placed on the upper surface BP1_USof the first lower pattern BP1 and the upper surface of the first fieldinsulating film 105. The first interface film 131 may wrap around thesheet pattern SP. The first interface film 131 may be placed between thesheet pattern SP and the bottom surface of the first gate electrode 120.The first interface film 131 may not extend along the side wall of thefirst gate spacer 140. Unlike the shown example, the first interfacefilm 131 may not extend along the upper surface of the first fieldinsulating film 105. The first interface film 131 extends along theupper surface of the first lower pattern BP1 and may not extend alongthe upper surface of the first field insulating film 105.

The first high dielectric constant film 132 may be placed on the firstinterface film 131. The first high dielectric constant film 132 may wraparound the first interface film 131. The first high dielectric constantfilm 132 may extend along the side walls and bottom surface of the firstgate electrode 120. The second gate insulating film 230 may extend alongthe side wall and bottom surface of the second gate electrode 220. Thesecond gate insulating film 230 may wrap around the wire pattern WP. Thesecond gate insulating film 230 may include a second interface film 231and a second high dielectric constant film 232.

As shown, the second interface film 231 may be placed on the uppersurface BP2_US of the second lower pattern BP2 and the upper surface ofthe second field insulating film 205. The second interface film 231 maywrap around the wire pattern WP. The second interface film 231 may beplaced between the wire pattern WP and the bottom surface of the secondgate electrode 220. The second interface film 231 may not extend alongthe side wall of the second gate spacer 240. Unlike the shown example,the second interface film 231 may not extend along the upper surface ofthe second field insulating film 205. The second interface film 231extends along the upper surface of the second lower pattern BP2, and maynot extend along the upper surface of the second field insulating film205.

The second high dielectric constant film 232 may be placed on the secondinterface film 231. The second high dielectric constant film 232 maywrap around the second interface film 231. The second high dielectricconstant film 232 may extend along the side walls and bottom surface ofthe second gate electrode 220. The second high dielectric constant film232 may wrap around the second interface film 231.

The first interface film 131 and the second interface film 231 mayinclude, for example, silicon oxide. The first high dielectric constantfilm 132 and the second high dielectric constant film 232 may include,for example, a high dielectric constant material having a higherdielectric constant than silicon oxide. The high dielectric constantmaterial may include, for example, one or more of boron nitride, hafniumoxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide,lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide,tantalum oxide, titanium oxide, barium strontium titanium oxide, bariumtitanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide,lead scandium tantalum oxide or lead zinc niobate.

The semiconductor device according to some other embodiments may includean NC (Negative Capacitance) FET using a negative capacitor. Forexample, the first gate insulating film 130 and the second gateinsulating film 230 may include a ferroelectric material film havingferroelectric properties, and a paraelectric material film havingparaelectric properties. For example, the ferroelectric material filmmay be configured to have a negative capacitance, and the paraelectricmaterial film may be configured to have a positive capacitance. Thus,when two or more capacitors are connected in series, and the capacitanceof each capacitor has a positive value, the entire capacitance decreasesfrom the capacitance of each individual capacitor. On the other hand,when at least one of the capacitances of two or more capacitorsconnected in series has a negative value, the entire capacitance may begreater than an absolute value of each individual capacitance, whilehaving a positive value.

When the ferroelectric material film having the negative capacitance andthe paraelectric material film having the positive capacitance areconnected in series, the overall capacitance values of the ferroelectricmaterial film and the paraelectric material film connected in series mayincrease. By the use of the increased overall capacitance value, atransistor including the ferroelectric material film may have asubthreshold swing (SS) below 60 mV/decade at room temperature.

The ferroelectric material film may have ferroelectric properties. Theferroelectric material film may include, for example, at least one ofhafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide,barium titanium oxide, and lead zirconium titanium oxide. Here, as anexample, the hafnium zirconium oxide may be a material obtained bydoping hafnium oxide with zirconium (Zr). As another example, thehafnium zirconium oxide may be a compound of hafnium (Hf), zirconium(Zr), and oxygen (O).

The ferroelectric material film may further include a dopant. Forexample, the dopant may include at least one of aluminum (Al), titanium(Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon(Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er),gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin(Sn). The type of dopant included in the ferroelectric material film mayvary, depending on which type of ferroelectric material is included inthe ferroelectric material film.

When the ferroelectric material film includes hafnium oxide, the dopantincluded in the ferroelectric material film may include, for example, atleast one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum(Al), and yttrium (Y). When the dopant is aluminum (Al), theferroelectric material film may include 3 to 8 atomic percent (at %)aluminum. Here, a ratio of the dopant may be a ratio of aluminum to thesum of hafnium and aluminum. In contrast, when the dopant is silicon(Si), the ferroelectric material film may include 2 to 10 atomic percentsilicon. When the dopant is yttrium (Y), the ferroelectric material filmmay include 2 to 10 atomic percent yttrium. When the dopant isgadolinium (Gd), the ferroelectric material film may include 1 to 7atomic percent gadolinium. When the dopant is zirconium (Zr), theferroelectric material film may include 50 to 80 atomic percentzirconium.

The paraelectric material film may have paraelectric properties. Theparaelectric material film may include at least one of, for example, asilicon oxide and a metal oxide having a high dielectric constant. Themetal oxide included in the paraelectric material film may include, forexample, but is not limited to, at least one of hafnium oxide, zirconiumoxide, and aluminum oxide.

The ferroelectric material film and the paraelectric material film mayinclude the same material. The ferroelectric material film has theferroelectric properties, but the paraelectric material film may nothave the ferroelectric properties. For example, when the ferroelectricmaterial film and the paraelectric material film include hafnium oxide,a crystal structure of hafnium oxide included in the ferroelectricmaterial film is different from a crystal structure of hafnium oxideincluded in the paraelectric material film.

The ferroelectric material film may have a thickness having theferroelectric properties. A thickness of the ferroelectric material filmmay be, but is not limited to, for example, 0.5 nm to 10 nm. Since acritical thickness that exhibits the ferroelectric properties may varyfor each ferroelectric material, the thickness of the ferroelectricmaterial film may vary depending on the ferroelectric material.

In some embodiments, the first gate insulating film 130 and the secondgate insulating film 230 may include a single ferroelectric materialfilm. In another embodiment, the first gate insulating film 130 and thesecond gate insulating film 230 may include a plurality of ferroelectricmaterial films spaced apart from each other. The first gate insulatingfilm 130 and the second gate insulating film 230 may have a stacked filmstructure in which a plurality of ferroelectric material films and aplurality of paraelectric material films are stacked in an alternatingarrangement of films.

The first gate capping pattern 150 may be placed on the upper surface ofthe first gate electrode 120 and the upper surface of the first gatespacer 140. Unlike the shown example, the first gate capping pattern 150may be placed between the first gate spacers 140. In such a case, theupper surface of the first gate capping pattern 150 may be placed in thesame plane as the upper surface of the first gate spacer 140. The uppersurface of the first gate capping pattern 150 may be an upper surface ofthe first gate structure GS1.

The second gate capping pattern 250 may be placed on the upper surfaceof the second gate electrode 220 and the upper surface of the secondgate spacer 240. Unlike the shown example, the second gate cappingpattern 250 may be placed between the second gate spacers 240. In such acase, the upper surface of the second gate capping pattern 250 may beplaced in the same plane as the upper surface of the second gate spacer240. The upper surface of the second gate capping pattern 250 may be anupper surface of the second gate structure GS2.

The first gate capping pattern 150 and the second gate capping pattern250 may include, for example, at least one of silicon nitride (SiN),silicon oxynitride (SiON), silicon oxide (SiO₂), silicon carbonitride(SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

A first source/drain pattern 170 may be formed on the first lowerpattern BP1. The first source/drain pattern 170 may be placed betweenthe first gate structures GS1. The first source/drain pattern 170 may beplaced on the side surface of the first gate structure GS1. The firstsource/drain pattern 170 may be placed between the adjacent first gatestructures GS1.

In some embodiments, the first source/drain pattern 170 may be placed onboth sides of the first gate structure GS1. Unlike the shown example,the first source/drain pattern 170 is located on one side of the firstgate structure GS1, but may not be placed on the other side of the firstgate structure GS1. In addition, a second source/drain pattern 270 maybe formed on the second lower pattern BP2. The second source/drainpattern 270 may be placed between the second gate structures GS2. Thesecond source/drain pattern 270 may be placed on the side surface of thesecond gate structure GS2. The second source/drain pattern 270 may beplaced between adjacent second gate structures GS2.

In other embodiments, the second source/drain pattern 270 may be placedon both sides of the second gate structure GS2. Unlike the shownexample, the second source/drain pattern 270 is located on one side ofthe second gate structure GS2, but may not be placed on the other sideof the second gate structure GS2.

The first source/drain pattern 170 and the second source/drain pattern270 may include an epitaxial pattern. That is, the first source/drainpattern 170 may be included in a source/drain region of a transistorthat uses the sheet pattern SP as a channel region. The secondsource/drain pattern 270 may be included in a source/drain region of atransistor that uses the wire pattern WP as the channel region.

In some embodiments, a first etching stop film 176 may be placed on theupper surface of the first source/drain pattern 170, the side wall ofthe first gate structure GS1, and the side wall of the firstsource/drain pattern 170. The first etching stop film 176 may extend tothe upper surface of the first gate capping pattern 150. A secondetching stop film 276 may be placed on the upper surface of the secondsource/drain pattern 270, the side wall of the second gate structureGS2, and the side wall of the second source/drain pattern 270. Althoughit is not shown, the first etching stop film 176 and the second etchingstop film 276 may not be formed.

The first etching stop film 176 and the second etching stop film 276 mayinclude, for example, a material having an etching selectivity withrespect to the first interlayer insulating film 190. The first etchingstop film 176 and the second etching stop film 276 may include, forexample, at least one of silicon nitride (SiN), silicon oxynitride(SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN),silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), andcombinations thereof.

A first active contact CA1 may be placed on the first active region RX1.A second active contact CA2 may be placed on the second active regionRX2. The first active contact CA1 may be connected to the firstsource/drain pattern 170 formed in the first active region RX1. Thesecond active contact CA2 may be connected to a second source/drainpattern 270 formed in the second active region RX2. In some embodiments,the first active contact CA1 may include a first lower active contact180 and a first upper active contact. Although it is not shown, thefirst upper active contact may be placed on the first lower activecontact 180.

The first lower active contact 180 may be formed on the firstsource/drain pattern 170. The first lower active contact 180 may beconnected to the first source/drain pattern 170. Although the uppersurface of the first lower active contact 180 is shown to be formedhigher than the upper surface of the gate electrode 120, this is onlyfor convenience of explanation, and the embodiment is not limitedthereto. The upper surface of the first lower active contact 180 may, ofcourse, be formed to be lower than the upper surface of the gateelectrode 120.

A first silicide film 175 may be formed between the first lower activecontact 180 and the first source/drain pattern 170. Although the firstsilicide film 175 is shown to be formed along a profile of an interfacebetween the first source/drain pattern 170 and the first lower activecontact 180, the embodiment is not limited thereto. The first silicidefilm 175 may include, for example, a metal silicide material.

The first lower active contact 180 may be formed of multiple films. Thefirst lower active contact 180 may include, for example, a first loweractive contact barrier film 180 a and a first lower active contactfilling film 180 b. The first lower active contact filling film 180 bmay be placed on the first lower active contact barrier film 180 a. Thefirst lower active contact barrier film 180 a may extend along the sidewalls and bottom surface of the first lower active contact filling film180 b.

The first lower active contact barrier film 180 a may include, forexample, at least one of tantalum (Ta), tantalum nitride (TaN), titanium(Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN),ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten(W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr),zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium(Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh)and a two-dimensional (2D) material. In the semiconductor deviceaccording to some embodiments, the two-dimensional material may be ametallic material and/or a semiconductor material. The two-dimensional(2D material) may include a two-dimensional allotrope or atwo-dimensional compound, and may include, but is not limited to, forexample, at least one of graphene, molybdenum disulfide (MoS₂),molybdenum diselenide (MoSe₂), tungsten diselenide (WSe₂), and tungstendisulfide (WS₂). That is, since the above-mentioned two-dimensionalmaterials are only listed by way of example, the two-dimensionalmaterials that may be included in the semiconductor device of thepresent disclosure are not limited by the above-mentioned materials. Afirst lower active contact filling film 180 b may include, for example,at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium(Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

The second active contact CA2 may include a second lower active contact280 and a second upper active contact 285. The description of the secondlower active contact 280 may be the same as the description of the firstlower active contact 180. A second silicide film 275 may be formedbetween the second lower active contact 280 and the second source/drainpattern 270. Although the second silicide film 275 is shown to be formedalong a profile of an interface between the second source/drain pattern270 and the second lower active contact 280, the embodiment is notlimited thereto. The second silicide film 275 may include, for example,a metal silicide material.

The second lower active contact 280 may be formed of multiple films. Thesecond lower active contact 280 may include, for example, a second loweractive contact barrier film 280 a and a second lower active contactfilling film 280 b. The second lower active contact filling film 280 bmay be placed on the second lower active contact barrier film 280 a. Thesecond lower active contact barrier film 280 a may be placed along theside walls and bottom surface of the second lower active contact fillingfilm 280 b.

The description of the materials included in the second lower activecontact barrier film 280 a and the second lower active contact fillingfilm 280 b may be the same as the description of the first lower activecontact barrier film 180 a and the first lower active contact fillingfilm 180 b.

The second upper active contact 285 may be placed on the second loweractive contact 280. The second upper active contact 285 may be connectedto the second lower active contact 280. That is, the second upper activecontact 285 may be connected to the second source/drain pattern 270. Thesecond upper active contact 285 may extend to the upper surface of thefirst interlayer insulating film 190. That is, the upper surface of thesecond upper active contact 285 may be placed on the same plane as theupper surface of the first interlayer insulating film 190, the uppersurface of the first gate contact 160, the upper surface of the secondgate capping pattern 250, and the upper surface of the first gatecapping pattern 150. In addition, the second upper active contact 285may be formed of multiple films. The second upper active contact 285 mayinclude, for example, a second upper active contact barrier film 285 aand a second upper active contact filling film 285 b. The second upperactive contact filling film 285 b may be placed on the second upperactive contact barrier film 285 a. The second upper active contactbarrier film 285 a may be placed along the side walls and bottom surfaceof the second upper active contact filling film 285 b. The descriptionof the materials included in the second upper active contact barrierfilm 285 a and the second upper active contact filling film 285 b may bethe same as the above description of the first lower active contactbarrier film 180 a and the first lower active contact filling film 180b.

The first gate contact 160 may be placed on the first active region RX1.The second gate contact 260 may be placed on the second active regionRX2. Since the first gate contact 160 and the second gate contact 260may be substantially the same, only the first gate contact 160 will bedescribed below. The first gate contact 160 may be placed inside thefirst gate structure GS1. The first gate contact 160 may be connected tothe first gate electrode 120 included in the first gate structure GS1.The first gate contact 160 may be formed to penetrate the first gatecapping pattern 150 in the third direction Z.

The first gate contact 160 may be placed at a position where it overlapsthe first gate structure GS1. In some embodiments, at least a part ofthe first gate contact 160 may be placed at a position where it overlapsthe sheet pattern SP. The upper surface of the first gate contact 160may be placed in the same plane as the upper surface of the first gatecapping pattern 150. The upper surface of the first gate contact 160 maybe located at the same plane as the upper surface of the second upperactive contact 285. The upper surface of the first gate contact 160 maybe located in the same plane as the upper surface of the firstinterlayer insulating film 190.

The first gate contact 160 may be formed of multiple films. The firstgate contact 160 may include, for example, a gate contact barrier film160 a and a gate contact filling film 160 b. The gate contact fillingfilm 160 b may be placed on the gate contact barrier film 160 a. Thegate contact barrier film 160 a may be placed along the side walls andbottom surface of the gate contact filling film 160 b. The contents ofthe materials included in the gate contact barrier film 160 a and thegate contact filling film 160 b may be the same as the description ofthe first lower active contact barrier film 180 a and the first loweractive contact filling film 180 b.

The first interlayer insulating film 190 may be formed on the firstsource/drain pattern 170, the second source/drain pattern 270, the firstfield insulating film 105, and the second field insulating film 205. Thefirst interlayer insulating film 190 may cover the side wall of thefirst lower active contact 180, the side wall of the second lower activecontact 280, and the side wall of the second upper active contact 285.The first interlayer insulating film 190 may include, for example, butis not limited to, Fluorinated TetraEthylOrthoSilicate (FTEOS), HydrogenSilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB),TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS),HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB),DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate(TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG(Fluoride Silicate Glass), polyimide nanofoams such as polypropyleneoxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate Glass),SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels,mesoporous silica or combinations thereof.

In some embodiments, a second interlayer insulating film 390 and a thirdinterlayer insulating film 490 may be formed on the first interlayerinsulating film 190. Each of the second interlayer insulating film 390and the third interlayer insulating film 490 may include, for example,at least one of silicon oxide, silicon nitride, silicon oxynitride and alow dielectric constant material.

In some embodiments, a wiring etching stop film 195 may extend along theupper surface of the first gate capping pattern 150, the upper surfaceof the first interlayer insulating film 190, the upper surface of thesecond gate capping pattern 250 and the upper surface of the secondupper active contact 285. In addition, the second interlayer insulatingfilm 390 may be placed on the wiring etching stop film 195. The wiringetching stop film 195 may include a material having an etchingselectivity with respect to the second interlayer insulating film 390.The wiring etching stop film 195 may include, for example, at least oneof silicon nitride (SiN), silicon oxynitride (SiON), siliconoxycarbonitride (SiOCN), silicon boronitride (SiBN), siliconoxyboronitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO),aluminum nitride (AlN), aluminum oxycarbide (AlOC) and a combinationthereof.

The first wiring pattern 310 may be placed on the first gate contact 160and the second upper active contact 285. The first wiring pattern 310may be connected to the first gate contact 160. The first wiring pattern310 may be connected to the second upper active contact 285. The firstwiring pattern 310 may be formed to penetrate the wiring etching stopfilm 195. The first wiring pattern 310 may be placed inside the secondinterlayer insulating film 390. The first wiring pattern 310 may includea portion that comes into direct contact with the second gate cappingpattern 250.

The first wiring pattern 310 may have a multiple conductive filmstructure. The first wiring pattern 310 may include, for example, afirst wiring barrier film 310 a and a first wiring filling film 310 b.The first wiring filling film 310 b may be placed on the first wiringbarrier film 310 a. The first wiring barrier film 310 a may be placedalong the side walls and bottom surface of the first wiring filling film310 b.

The first wiring barrier film 310 a may include, for example, at leastone of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titaniumnitride (TiN), titanium silicon nitride (TiSiN), nickel (Ni), nickelboron (NiB), tungsten nitride (WN), tungsten carbonitride (WCN),zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride(VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir),rhodium (Rh), and a two-dimensional (2D) material. In contrast, thefirst wiring filling film 310 b may include, for example, at least oneof aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium(Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

In some embodiments, a via structure 410 and a second wiring pattern 420may be included on the first wiring pattern 310. The via structure 410and the second wiring pattern 420 may be placed inside the thirdinterlayer insulating film 490.

The via structure 410 may be formed on the first wiring pattern 310. Thevia structure 410 may be connected to the first wiring pattern 310. Thevia structure 410 may be multiple films including a via barrier film 410a and a via filling film 410 b. The via filling film 410 b may be placedon the via barrier film 410 a. The via barrier film 410 a may be placedalong the side walls and bottom surface of the via filling film 410 b.

The via barrier film 410 a may include, for example, at least one oftantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride(TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co),nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN),tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN),vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride(NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional(2D) material. In contrast, the via filling film 410 b may include, forexample, at least one of aluminum (Al), copper (Cu), tungsten (W),cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), andmolybdenum (Mo).

The second wiring pattern 420 may be placed on the via structure 410.The second wiring pattern 420 may be multiple films including a secondwiring barrier film 420 a and a second wiring filling film 420 b. Thesecond wiring filling film 420 b may be placed on the second wiringbarrier film 420 a. The second wiring barrier film 420 a may be placedalong the side walls and bottom surface of the second wiring fillingfilm 420 b. Contents of the materials included in the second wiringbarrier film 420 a and the second wiring filling film 420 b may be thesame as the description of the materials included in the first wiringbarrier film 310 a and the first wiring filling film 310 b.

FIG. 4 is an enlarged view of a region P and a region Q of FIG. 2 . FIG.5 is an enlarged view of a region R and a region S of FIG. 3 .Hereinafter, the sheet pattern SP, the wire pattern WP, the first gateinsulating film 130, and the second gate insulating film 230 will bedescribed in a more detail referring to FIGS. 4 and 5 .

Referring to FIGS. 4 and 5 , a total thickness (t1+t3) of the first gateinsulating film 130 may be smaller than a total thickness (t2+t4) of thesecond gate insulating film 230. In some embodiments, a thickness t1 ofthe first interface film 131 may be smaller than a thickness t2 of thesecond interface film 231. As described above, a first drive voltage ofthe transistor of the first region I may be lower than a second drivevoltage of the transistor of the second region II. Therefore, thethickness t1 of the first interface film 131 may be smaller than thethickness t2 of the second interface film 231.

A thickness t3 of the first high dielectric constant film 132 may be thesame as a thickness t4 of the second high dielectric constant film 232.The first high dielectric constant film 132 and the second highdielectric constant film 232 may be formed at the same level. As usedherein, the term “same level” means formation by the same fabricatingprocess. That is, since the thickness t1 of the first interface film 131is smaller than the thickness t2 of the second interface film 231, andthe thickness t3 of the first high dielectric constant film 132 is thesame as the thickness t4 of the second high dielectric constant film232, the total thickness (t1+t3) of the first gate insulating film 130is smaller than the total thickness (t2+t4) of the second gateinsulating film 230.

In some embodiments, a distance d1 at which the sheet pattern SP isseparated in the third direction Z may be smaller than a distance d2 atwhich the wire pattern WP is separated in the third direction Z. Thatis, the distance d1 at which the first sheet pattern SP1 and the secondsheet pattern SP2 are separated may be smaller than the distance d2 atwhich the first wire pattern WP1 and the second wire pattern WP2 areseparated. Because the distance d2 at which the first wire pattern WP1and the second wire pattern WP2 are separated from each other is greaterthan the distance d1 at which the first sheet pattern SP1 and the secondsheet pattern SP2 are separated from each other, it is possible toeasily form the second interface film 231 as a relatively thick film.

In some embodiments, a height H3 from a reference plane RP to the uppersurface of the first sheet pattern SP1 may be greater than is a heightH4 from the reference plane RP to the upper surface of the first wirepattern WP1. Here, the reference plane RP may be a virtual plane thatpasses through a center of the first sheet pattern SP1 and a center ofthe first wire pattern WP1. The reference plane RP may extend in thefirst direction X and the second direction Y. That is, a width of thesheet pattern SP in the third direction Z may be greater than a width ofthe wire pattern WP in the third direction Z.

In some embodiments, an upper surface BP1_US of the first lower patternBP1 may be placed in the same plane as an upper surface BP2_US of thesecond lower pattern BP2. A height H5 in the third direction Z from theupper surface BP1_US of the first lower pattern BP1 to the referenceplane RP may be the same as a height H6 from the upper surface BP2_US ofthe second lower pattern BP2 to the reference plane RP. However, thetechnical idea of the present disclosure is not limited thereto.

In some embodiments, the width of the sheet pattern SP in the firstdirection X may be the same as the width of the wire pattern WP in thefirst direction X. The width of the sheet pattern SP in the seconddirection Y may be greater than the width of the wire pattern WP in thesecond direction Y.

In some embodiments, a width W3 of the upper surface BP1_US of the firstlower pattern BP1 in the second direction Y may be greater than a widthW4 of the upper surface BP2_US of the second lower pattern BP2 in thesecond direction Y. However, the technical idea of the presentdisclosure is not limited thereto. The width W3 of the upper surfaceBP1_US of the first lower pattern BP1 in the second direction Y may bethe same as the width W4 of the upper surface BP2_US of the second lowerpattern BP2 in the second direction Y.

FIG. 6 is an enlarged view of a region T of FIG. 5 . Hereinafter, thewire pattern will be described in more detail referring to FIG. 6 .Referring to FIG. 6 , the wire pattern WP may include a first wirepattern WP1, a second wire pattern WP2, and a third wire pattern WP3.The first wire pattern WP1 to the third wire pattern WP3 may be placedsequentially. That is, the second wire pattern WP2 may be locatedbetween the first wire pattern WP1 and the third wire pattern WP3.

In some embodiments, the first wire pattern WP1 may have a semi-circularshape from the viewpoint of the cross-sectional area. For example, thefirst wire pattern WP1 may include a first surface WP1_a extending inthe second direction Y, and a second surface WP1_b having a concavecurved surface with respect to the first surface WP1_a on the firstsurface WP1_a. The second surface WP1_b may be in contact with both endsof the first surface WP1_a. The second surface WP1_b may have a concavecurved surface with respect to the second lower pattern BP2. The firstsurface WP1_a of the first wire pattern WP1 may be, for example, asemicircular diameter. The second surface WP2_b of the first wirepattern WP1 may be, for example, a semicircular arc. From the viewpointof the cross-sectional area, the second wire pattern WP2 may include afirst sub-wire pattern WP2_1 and a second sub-wire pattern WP2_2. Thesecond sub-wire pattern WP2_2 may be placed on the first sub-wirepattern WP2_1. The width of the first sub-wire pattern WP2_1 in thesecond direction Y may gradually increase as its distance from the firstwire pattern WP1 increases. The width of the second sub-wire patternWP2_2 in the second direction Y may gradually decrease as its distancefrom the first wire pattern WP1 increases.

The width of the first sub-wire pattern WP2_1 in the second direction Ymay gradually increase as its distance from the second lower pattern BP2increases. The width of the second sub-wire pattern WP2_2 in the seconddirection Y may gradually decrease as its distance from the second lowerpattern BP2 increases. A height H1 of the first sub-wire pattern WP2_1in the third direction Z may be smaller than a height H2 of the firstsub-wire pattern WP2_2 in the third direction Z. However, the technicalidea of the present disclosure is not limited thereto.

The second wire pattern WP2 may have a third surface WP2_a and a fourthsurface WP2_b. The fourth surface WP2_b may be placed on the thirdsurface WP2_a. The third surface WP2_a and the fourth surface WP2_b maybe connected to each other. The third surface WP2_a may be a convexcurved surface with respect to the first wire pattern WP1. The fourthsurface WP2_b may be a concave curved surface with respect to the firstwire pattern WP1. A length of the third surface WP2_a may be shorterthan a length of the fourth surface WP2_b. However, the technical ideaof the present disclosure is not limited thereto.

From the viewpoint of the cross-sectional area, the third wire patternWP3 may have an elliptical shape. The third wire pattern WP3 may have anelliptical shape in which the width W1 in the second direction Y issmaller than the width W2 in the third direction Z. The third wirepattern WP3 may have a fifth surface WP3_a and a sixth surface WP3_b.The fifth surface WP3_a may be a convex curved surface with respect tothe first wire pattern WP1. The sixth surface WP3_b may be a concavecurved surface with respect to the first wire pattern WP1. A length ofthe fifth surface WP3_a may be the same as a length of the sixth surfaceWP3_b, but is not limited thereto.

In some embodiments, the volume of the first wire pattern WP1 may begreater than the volumes of the second wire pattern WP2 and the thirdwire pattern WP3. The volume of the second wire pattern WP2 may begreater than the volume of the third wire pattern WP3. However, thetechnical idea of the present disclosure is not limited thereto.

FIG. 7 is a diagram for explaining the semiconductor device according tosome embodiments. For convenience of explanation, points different fromcontents described using FIGS. 1 to 6 will be mainly described. Forreference, FIG. 7 may be a cross-sectional view taken along lines C-C′and D-D′ of FIG. 1 . Referring to FIG. 7 , the side wall BP2_SW of thesecond lower pattern BP2 may include a curved line.

The second lower pattern BP2 may include a first portion BP2_1 thatoverlaps the second field insulating film 205 in the second direction Y,and a second portion BP2_2 that does not overlap the second fieldinsulating film 205 in the second direction Y. The side wall BP2_SW ofthe second lower pattern BP2 may include a side wall BP2_SW1 of thefirst portion BP2_1 of the second lower pattern BP2, and a side wallBP2_SW2 of the second portion BP2_2 of the second lower pattern BP2.

The side wall BP2_SW1 of the first portion BP2_1 of the second lowerpattern BP2 may be a straight line. The side wall BP2_SW2 of the secondportion BP2_2 of the second lower pattern BP2 may be a curved line. Aslope of the side wall BP2_SW1 of the first portion BP2_1 of the secondlower pattern BP2 may be different from a slope of the side wall BP2_SW2of the second portion BP2_2 of the second lower pattern BP2. In theprocess of forming the wire pattern WP, a part of the second lowerpattern BP2 may be removed. In the process of forming the wire patternWP, a part of the second portion BP2_2 of the second lower pattern BP2may be removed. However, the technical idea of the present disclosure isnot limited thereto.

FIG. 8 is a diagram for explaining a semiconductor device according tosome embodiments. For convenience of explanation, points different fromcontents described using FIGS. 1 to 6 will be mainly described. Forreference, FIG. 8 may be a cross-sectional view taken along lines C-C′and D-D′ of FIG. 1 . Referring to FIG. 8 , a width W5 of the first sheetpattern SP1 in the second direction Y may be different from a width W6of the second sheet pattern SP2 and the third sheet pattern SP3 in thesecond direction Y. The width W6 of the second sheet pattern SP2 in thesecond direction Y may be the same as the width W6 of the third sheetpattern SP3 in the second direction Y. On the other hand, the width W5of the first sheet pattern SP1 in the second direction Y may be greaterthan the width W6 of the second sheet pattern SP2 and the third sheetpattern SP3 in the second direction Y.

FIG. 9 is a diagram for explaining a semiconductor device according tosome embodiments. For convenience of explanation, points different fromcontents described using FIGS. 1 to 6 will be mainly described. Forreference, FIG. 9 may be a cross-sectional view taken along lines C-C′and D-D′ of FIG. 1 . Referring to FIG. 9 , the first to third wirepatterns WP1 to WP3 according to some embodiments may all have the sameshape. Each of the first to third wire patterns WP1 to WP3 may all have,for example, a circular shape. The volumes of each of the first to thirdwire patterns WP1 to WP3 may all be the same. However, the technicalidea of the present disclosure is not limited thereto. The first tothird wire patterns WP1 to WP3 may, of course, have an elliptical shape.

FIG. 10 is a diagram for explaining the semiconductor device accordingto some embodiments. For convenience of explanation, points differentfrom contents described using FIGS. 1 to 6 and 9 will be mainlydescribed. For reference, FIG. 10 may be a cross-sectional view takenalong lines C-C′ and D-D′ of FIG. 1 .

Referring to FIG. 10 , the wire pattern WP according to some embodimentsmay have different sizes. For example, from the viewpoint of thecross-sectional area, the size of the first wire pattern WP1 may begreater than the sizes of the second wire pattern WP2 and the third wirepattern WP3. The size of the second wire pattern WP2 may be greater thanthe size of the third wire pattern WP3. That is, the size of the wirepattern WP may gradually decrease as its distance from the second lowerpattern BP2 increases. In some embodiments, the volume of the first wirepattern WP1 may be greater than the volumes of the second wire patternWP2 and the third wire pattern WP3. The volume of the second wirepattern WP2 may be greater than the volume of the third wire patternWP3.

FIG. 11 is a diagram for explaining a semiconductor device according tosome embodiments. FIG. 12 is a diagram for explaining a semiconductordevice according to some embodiments. For convenience of explanation,points different from contents described using FIGS. 1 to 6 will bemainly described. For reference, FIG. 11 may be a cross-sectional viewtaken along lines A-A′ and B-B′ of FIG. 1 . FIG. 12 may be across-sectional view taken along lines C-C′ and D-D′ of FIG. 1 .

Referring to FIG. 11 and FIG. 12 , the upper surface BP1_US of the firstlower pattern BP1 and the upper surface BP2_US of the second lowerpattern BP_2 may not be located in the same plane. The upper surfaceBP1_US of the first lower pattern BP1 may be formed to be higher thanthe upper surface BP2_US of the second lower pattern BP_2. As anexample, a height H7 from the upper surface 150_US of the first gatecapping pattern 150 to the upper surface BP1_US of the first lowerpattern BP1 may be smaller than a height H8 from the upper surface250_US of the second gate capping pattern 250 to the upper surfaceBP2_US of the second lower pattern BP2. The upper surface 150_US of thefirst gate capping pattern 150 may be located in the same plane as theupper surface 250_US of the second gate capping pattern 250.Accordingly, the upper surface 150_US of the first gate capping pattern150 may be higher than the upper surface BP2_US of the second lowerpattern BP2.

The height from the upper surface of the first substrate 100 to theupper surface BP1_US of the first lower pattern BP1 may be greater thanthe height from the upper surface of the second substrate 200 to theupper surface BP2_US of the second lower pattern BP_2. A height of thefirst lower pattern BP1 in the third direction Z may be greater than theheight of the second lower pattern BP2 in the third direction Z. In theprocess of forming the wire pattern WP, a part of the second lowerpattern BP2 is removed, and the upper surface BP2_US of the second lowerpattern BP2 may be lowered.

FIG. 13 is a diagram for explaining a semiconductor device according tosome embodiments. For convenience of explanation, points different fromcontents described using FIGS. 1 to 6 will be mainly described. Forreference, FIG. 13 may be a cross-sectional view taken along lines A-A′and B-B′ of FIG. 1 . Referring to FIG. 13 , a first interface film 131on the sheet pattern SP may be placed in a ‘U’ shape. A second interfacefilm 231 on the wire pattern WP may be placed in a ‘U’ shape. The firstinterface film 131 may be placed on the side wall of the first gatespacer 140. The first interface film 131 may be placed between the sidewall of the first gate spacer 140 and the first high dielectric constantfilm 132. The second interface film 231 may be placed on the side wallof the second gate spacer 240. The second interface film 231 may beplaced between the side wall of the second gate spacer 240 and thesecond high dielectric constant film 232.

FIG. 14 is a diagram for explaining a semiconductor device according tosome embodiments. For convenience of explanation, points different fromcontents described using FIGS. 1 to 6 will be mainly described. Forreference, FIG. 14 may be a cross-sectional view taken along lines A-A′and B-B′ of FIG. 1 . Referring to FIG. 14 , the first gate spacer 140may include a first outer spacer 141 and a first inner spacer 142. Thesecond gate spacer 240 may include a second outer spacer 241 and asecond inner spacer 242.

The first inner spacer 142 may be placed between the first source/drainpatterns 170. The second inner spacer 242 may be placed between thesecond source/drain patterns 270. The first inner spacer 142 and thesecond inner spacer 242 may include, for example, at least one ofsilicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO₂),silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), siliconoxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinationsthereof.

The first interface film 131 may not extend along the side wall of thefirst inner spacer 142 between the first source/drain patterns 170. Thefirst interface film 131 may be placed between the sheet pattern SP andthe first high dielectric constant film 132, or between the first lowerpattern BP1 and the first high dielectric constant film 132. The secondinterface film 231 may not extend along the side wall of the secondinner spacer 242 between the second source/drain patterns 270. Thesecond interface film 231 may be placed between the wire pattern WP andthe second high dielectric constant film 232, or between the secondlower pattern BP2 and the second high dielectric constant film 232.

FIG. 15 is a diagram for explaining a semiconductor device according tosome embodiments. For convenience of explanation, points different fromcontents described using FIGS. 1 to 6 and 14 will be mainly described.For reference, FIG. 15 may be a cross-sectional view taken along linesA-A′ and B-B′ of FIG. 1 . Referring to FIG. 15 , the first interfacefilm 131 on the sheet pattern SP may be placed in a ‘U’ shape. Thesecond interface film 231 on the wire pattern WP may be placed in a CU′shape.

The first interface film 131 may be placed on the side wall of the firstouter spacer 141. The first interface film 131 may extend along the sidewalls of the sheet pattern SP and the first outer spacer 141. The firstinterface film 131 may be placed on the side wall of the first innerspacer 142. The first interface film 131 may wrap around the first highdielectric constant film 132.

The second interface film 231 may be placed on the side wall of thesecond outer spacer 241. The second interface film 231 may extend alongthe side walls of the wire pattern WP and the second outer spacer 241.The second interface film 231 may be placed on the side wall of thesecond inner spacer 242. The second interface film 231 may wrap aroundthe second high dielectric constant film 232.

FIG. 16 is a diagram for explaining a semiconductor device according tosome embodiments. FIG. 17 is a diagram for explaining a semiconductordevice according to some embodiments. For convenience of explanation,points different from contents described using FIGS. 1 to 6 will bemainly described. For reference, FIG. 16 may be a cross-sectional viewtaken along lines A-A′ and B-B′ of FIG. 1 . FIG. 17 may be across-sectional view taken along lines C-C′ and D-D′ of FIG. 1 .

Referring to FIGS. 16 and 17 , the number of sheet patterns SP may begreater than the number of wire patterns WP. The sheet patterns SP mayinclude a first sheet pattern SP1, a second sheet pattern SP2, a thirdsheet pattern SP3, and a fourth sheet pattern SP4 which are sequentiallyplaced on the first lower pattern BP1. The first sheet pattern SP1 maybe located between the first lower pattern BP1 and the second sheetpattern SP2. The second sheet pattern SP2 may be located between thethird sheet pattern SP3 and the first sheet pattern SP1. The third sheetpattern SP3 may be located between the fourth sheet pattern SP4 and thesecond sheet pattern SP2. Moreover, although the number of sheetpatterns SP is shown as four, and the number of wire patterns WP isshown as three, this is only for convenience of explanation, and thenumbers thereof are not limited thereto.

FIGS. 18 to 33 are cross-sectional views of intermediate structures thatillustrate methods of fabricating semiconductor devices according tosome embodiments of the present disclosure. Referring to FIG. 18 , afirst lower pattern BP1 may be formed on the first substrate 100 of thefirst region I. A first field insulating film 105 may be formed on bothsides of the first lower pattern BP1. A first mold film 510 and apre-sheet pattern 520 may be sequentially stacked on the first lowerpattern BP1. Although the numbers of first mold films 510 and pre-sheetpatterns 520 are shown as three, this is only for convenience ofexplanation, and the numbers thereof are not limited thereto.

A second lower pattern BP2 may be formed on the second substrate 200 ofthe second region II. A second field insulating film 205 may be formedon both sides of the second lower pattern BP2. A second mold film 610and a pre-wire pattern 620 may be sequentially stacked on the secondlower pattern BP2. Although the numbers of second mold films 610 andpre-wire patterns 620 are shown as three, this is only for convenienceof explanation, and the numbers thereof are not limited thereto.

In some embodiments, the thickness of the first mold film 510 and thesecond mold film 610 may be, for example, 10 nm to 50 nm. The first moldfilm 510 and the second mold film 610 may be formed at the same level.The pre-sheet pattern 520 and the pre-wire pattern 620 may be formed atthe same level. However, the technical idea of the present disclosure isnot limited thereto. Of course, the thickness of the first mold film 510and the thickness of the second mold film 610 may be different from eachother. Although the thicknesses of the first mold film 510 and thesecond mold film 610 are shown as being different from the thicknessesof the pre-sheet pattern 520 and the pre-wire pattern 620, this is onlyfor convenience of explanation, and the embodiment is not limitedthereto. The thicknesses of the first mold film 510 and the second moldfilm 610 may be the same as the thicknesses of the pre-sheet pattern 520and the pre-wire pattern 620.

The first mold film 510 and the second mold film 610 may include, forexample, silicon germanium (SiGe). The pre-sheet pattern 520 and thepre-wire pattern 620 may include, for example, silicon (Si). In someembodiments, the concentration of germanium (Ge) included in the firstmold film 510 and the second mold film 610 may be 10% to 90%. Theconcentration of germanium (Ge) included in the first mold film 510 maybe the same as the concentration of germanium (Ge) included in thesecond mold film 610. However, the technical idea of the presentdisclosure is not limited thereto. The concentration of germanium (Ge)included in the first mold film 510 may, of course, differ from theconcentration of germanium (Ge) included in the second mold film 610.

Referring to FIG. 19 , in the second region II, a protective film 700may be formed on the side wall of the second mold film 610, the sidewall of the pre-wire pattern 620, and the upper surface of the pre-wirepattern 620. The protective film 700 may protect the pre-wire pattern620 when the sheet pattern is formed. The protective film 700 mayinclude, for example, but is not limited to, silicon (Si).

Referring to FIG. 20 , in the second region II, a first sacrificial film810 may be formed on the second field insulating film 205 and theprotective film 700. The first sacrificial film 810 may protect thepre-wire pattern 620 when the sheet pattern is formed. The firstsacrificial film 810 may include, for example, but is not limited to,silicon oxide. Unlike the shown example, the first sacrificial film 810may not be formed.

Referring to FIG. 21 , the sheet pattern SP may be formed by removingthe first mold film 510. The first mold film 510 may be selectivelyremoved by utilizing the process of selectively removing silicongermanium. That is, silicon germanium may be removed, but silicon maynot be removed.

In some embodiments, the sheet pattern closest to the first lowerpattern BP1 may be the first sheet pattern SP1. The second sheet patternSP2 may be formed on the first sheet pattern SP1. The second sheetpattern SP2 may be spaced apart from the first sheet pattern SP1 in thethird direction Z. The third sheet pattern SP3 may be formed on thesecond sheet pattern SP2. The third sheet pattern SP3 may be spacedapart from the second sheet pattern SP2 in the third direction Z.

Referring to FIG. 22 , the protective film 700 and the first sacrificialfilm 810 may be removed. The first sacrificial film 810 may be removedto expose the protective film 700. Subsequently, the protective film 700may be removed to expose the second mold film 610 and the pre-wirepattern 620.

Referring to FIG. 23 , in the first region I, a second sacrificial film820 that wraps the sheet pattern SP may be formed on the first fieldinsulating film 105 and the first lower pattern BP1. The secondsacrificial film 820 may protect the sheet pattern SP in the process offorming the wire pattern (e.g., WP of FIG. 28 ). The second sacrificialfilm 820 may include, for example, silicon oxide, silicon nitride, and acombination film thereof. The second sacrificial film 820 may include,for example, but is not limited to, SOH.

Referring to FIG. 24 , an oxidation process may be performed in thesecond region II. As the oxidation process is performed, an oxide film900 is formed along the side wall of the second mold film 610, the sidewall of the pre-wire pattern 620, and the upper surface of the pre-wirepattern 620. The oxide film 900 may be formed, while oxidizing thesecond mold film 610 or the pre-wire pattern 620. The oxide film 900 mayinclude silicon oxide (SiO₂). Moreover, silicon germanium (SiGe)included in the second mold film 610 may be oxidized to form silicongermanium oxide (SiGeO). Subsequently, the silicon germanium oxide(SiGeO) may be oxidized to form silicon oxide (SiO₂) and germanium (Ge).Germanium (Ge) may be diffused toward the pre-wire pattern 620. Silicon(Si) included in the pre-wire pattern 620 may be oxidized to formsilicon oxide (SiO₂).

The oxidation process may include, for example, at least one of a dryoxygen (O₂) annealing process of 500° C. or higher, a wet annealingprocess of 400° C. or higher, and ozone (O₃) and hydrogen peroxide(H₂O₂) annealing process of 300° C. or higher. However, the technicalidea of the present disclosure is not limited thereto.

Referring to FIG. 25 , the thickness of the oxide film 900 may furtherincrease. For example, as the oxidation process is performed, an amountof oxidation of silicon germanium (SiGe) included in the second moldfilm 610 may increase. The amount of oxidation of silicon (Si) includedin the pre-wire pattern 620 may increase. As the amount of oxidation ofthe second mold film 610 and the pre-wire pattern 620 increases, thethickness of the oxide film 900 may gradually increase. And, as theamount of oxidation of the pre-wire pattern 620 increases, the width ofthe pre-wire pattern 620 may gradually decrease.

Referring to FIG. 26 , germanium (Ge) generated with oxidation of thesecond mold film 610 is may be diffused. Germanium (Ge) may be diffusedtoward the pre-wire pattern 620. Silicon (Si) included in the pre-wirepattern 620 and diffused germanium (Ge) may be combined to form silicongermanium (Ge). That is, the cross-sectional area of the pre-wirepattern 620 may decrease from the viewpoint of the cross-sectional area.The cross-sectional area of the second mold film 610 may increase.

Referring to FIG. 27 , the cross-sectional area of the pre-wire pattern620 may decrease from the viewpoint of the cross-sectional area.Germanium (Ge) formed with oxidation of the second mold film 610 may bediffused into the pre-wire pattern 620. The silicon (Si) included in thepre-wire pattern 620 may be combined with the diffused germanium (Ge).

Referring to FIG. 28 , the second mold film 610 may be removed to form awire pattern WP. The second mold film 610 may be selectively removed byutilizing the process of selectively removing silicon germanium (Ge).Silicon germanium (Ge) may be removed and silicon (Si) may not beremoved. The wire pattern closest to the second lower pattern BP2 may bethe first wire pattern WP1. The second wire pattern WP2 may be formed onthe first wire pattern WP1. The second wire pattern WP2 may be spacedapart from the first wire pattern WP1 in the third direction Z. Thethird wire pattern WP3 may be formed on the second wire pattern WP2. Thethird wire pattern WP3 may be spaced apart from the second wire patternWP2 in the third direction Z.

Referring to FIGS. 6 and 28 , the first wire pattern WP1 may have asemi-circular shape. The second wire pattern WP2 may have an ellipticalshape. The third wire pattern WP3 may have an elliptical shape. However,the technical idea of the present disclosure is not limited thereto. Theshape of the wire pattern WP may vary, depending on the extent to whichthe oxidation process is performed.

Referring to FIG. 29 , the second interface film 231 may be formed onthe upper surface of the second lower pattern BP2 and the upper surfaceof the second field insulating film 205 in the second region II. Thesecond interface film 231 may wrap around the wire pattern WP. Referringto FIG. 30 , a third sacrificial film 830 that completely covers thesecond interface film 231 may be formed in the second region II. Thethird sacrificial film 830 may be used to selectively form the firstinterface film 131 in the first region I. The third sacrificial film 830may include, for example, silicon oxide, silicon nitride, and acombination film thereof. Referring to FIG. 31 , the first interfacefilm 131 may be formed on the upper surface of the first lower patternBP1 and the upper surface of the first field insulating film 105 in thefirst region I. The first interface film 131 may wrap around the sheetpattern SP. Referring to FIG. 32 , the third sacrificial film 830 may beremoved. Subsequently, the first high dielectric constant film 132 maybe formed on the first interface film 131. A second high dielectricconstant film 232 may be formed on the second interface film 231. Thefirst high dielectric constant film 132 and the second high dielectricconstant film 232 may be formed at the same level, and the thickness ofthe first high dielectric constant film 132 may be the same as thethickness of the second high dielectric constant film 232.

Referring to FIG. 33 , the first gate electrode 120 may be formed on thefirst high dielectric constant film 132 in the first region I. Thesecond gate electrode 220 may be formed on the second high dielectricconstant film 232 in the second region II. The first gate electrode 120and the second gate electrode 220 may be formed at the same level.

In concluding the detailed description, those skilled in the art willappreciate that many variations and modifications may be made to thepreferred embodiments without substantially departing from theprinciples of the present disclosure. Therefore, the disclosed preferredembodiments of the disclosure are used in a generic and descriptivesense only and not for purposes of limitation.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate having first and second regions therein; a firstlower semiconductor pattern, which protrudes from the semiconductorsubstrate in the first region and extends in a first direction acrossthe semiconductor substrate; a first gate electrode, which extendsacross the first lower semiconductor pattern and the semiconductorsubstrate in a second direction orthogonal to the first direction; aplurality of semiconductor sheet patterns, which are spaced apart fromeach other in a third direction orthogonal to the first and seconddirections to thereby define a vertical stack of semiconductor sheetpatterns, on the first lower semiconductor pattern; a first gateinsulating film which separates the plurality of semiconductor sheetpatterns from the first gate electrode; a second lower semiconductorpattern, which protrudes from the semiconductor substrate in the secondregion and extends in the first direction across the semiconductorsubstrate; a plurality of wire patterns spaced apart from each other inthe third direction, on the second lower semiconductor pattern; and asecond gate insulating film wrapped around each of the plurality of wirepatterns; wherein a thickness of the first gate insulating film lessthan a thickness of the second gate insulating film; and wherein anaverage thickness of the plurality of sheet patterns, as measured in thethird direction, is greater than average thickness of the plurality ofwire patterns, as measured in the third direction.
 2. The semiconductordevice of claim 1, further comprising: a field insulating film extendingon opposing sides of the second lower semiconductor pattern; wherein thesecond lower semiconductor pattern includes a first portion whichoverlaps the field insulating film in the second direction, and a secondportion extending on the first portion; and wherein a slope of a sidewall of the second portion of the second lower semiconductor pattern isunequal to a slope of a side wall of the first portion of the secondlower semiconductor pattern.
 3. The semiconductor device of claim 1,wherein a width of an upper surface of the first lower semiconductorpattern in the second direction is greater than a width of the secondlower semiconductor pattern in the second direction.
 4. Thesemiconductor device of claim 1, wherein an upper surface of the firstlower semiconductor pattern is coplanar with an upper surface of thesecond lower semiconductor pattern.
 5. The semiconductor device of claim1, wherein a number of the plurality of sheet patterns is greater than anumber of the plurality of wire patterns.
 6. The semiconductor device ofclaim 1, wherein the first gate insulating film includes a firstinterface film, and a first high dielectric constant film on the firstinterface film, wherein the second gate insulating film includes asecond interface film, and a second high dielectric constant film on thesecond interface film, and wherein the first interface film is thinnerthan the second interface film.
 7. The semiconductor device of claim 6,wherein the first high dielectric constant film and the second highdielectric constant film have the same thickness.
 8. The semiconductordevice of claim 1, wherein the plurality of semiconductor sheet patternsincludes a first sheet pattern and a second sheet pattern; and whereinthe first sheet pattern is located between the second sheet pattern andthe first lower semiconductor pattern; and wherein a width of the firstsheet pattern is greater than a width of the second sheet pattern, asmeasured in the second direction.
 9. The semiconductor device of claim1, wherein the plurality of wire patterns includes a first wire patternand a second wire pattern, which is located between the second wirepattern and the second lower semiconductor pattern; and wherein across-sectional area of the first wire pattern is greater than across-sectional area of the second wire pattern.
 10. A semiconductordevice comprising: a first lower semiconductor pattern, which protrudesfrom a first region of a substrate and extends lengthwise in a firstdirection across the substrate; a first gate electrode, which extendsacross the first lower semiconductor pattern and the substrate in asecond direction orthogonal to the first direction; a plurality ofsemiconductor sheet patterns, which are spaced apart from each other ina third direction orthogonal to the first and second directions tothereby define a vertical stack of semiconductor sheet patterns, on thefirst lower semiconductor pattern; a first gate insulating film whichseparates the plurality of semiconductor sheet patterns from the firstgate electrode, said first gate insulating film including a firstinterface film, and a first high dielectric constant film on the firstinterface film; a second lower semiconductor pattern, which protrudesfrom a second region of a substrate and extends lengthwise in the firstdirection across the substrate; a second gate electrode, which extendsacross the second lower semiconductor pattern and the substrate in thesecond direction; a plurality of wire patterns spaced apart from eachother in the third direction, on the second lower semiconductor pattern;and a second gate insulating film wrapped around each of the pluralityof wire patterns, said second gate insulating film including a secondinterface film, and a second high dielectric constant film on the secondinterface film; wherein the second interface film is thicker than thefirst interface film.
 11. The semiconductor device of claim 10, whereina thickness of the first high dielectric constant film is equal to athickness of the second high dielectric constant film.
 12. Thesemiconductor device of claim 10, further comprising: a field insulatingfilm extending on both sides of the second lower semiconductor pattern;wherein the second lower semiconductor pattern includes a first portionwhich overlaps the field insulating film in the second direction, and asecond portion extending on the first portion; and wherein a slope of aside wall of the second portion of the second lower semiconductorpattern is unequal to a slope of a side wall of the first portion of thesecond lower semiconductor pattern.
 13. The semiconductor device ofclaim 10, wherein the plurality of wire patterns includes a first wirepattern and a second wire pattern; wherein the first wire patternextends between the second lower semiconductor pattern and the secondwire pattern; and wherein cross-sectional area of the first wire patternis greater than a cross-sectional area of the second wire pattern. 14.The semiconductor device of claim 10, wherein a width of an uppersurface of the first lower semiconductor pattern is greater than a widthof an upper surface of the second lower semiconductor pattern, asmeasured in the second direction.
 15. A semiconductor device,comprising: a first lower semiconductor pattern, which protrudes from afirst region of a substrate and extends lengthwise in a first directionacross the substrate; a first gate electrode, which crosses the firstlower semiconductor pattern in a second direction, which is orthogonalto the first direction; first to third sheet patterns, which arevertically stacked on the first lower semiconductor pattern, and spacedapart from the first lower semiconductor pattern in a third directionorthogonal to the first direction and the second direction; a first gateinsulating film, which surrounds the first to third sheet patterns, andincludes a first interface film, and a first high dielectric constantfilm on the first interface film; a second lower semiconductor pattern,which protrudes from a second region of the substrate and extendslengthwise in the first direction across the substrate; a second gateelectrode extending in the second direction on the second lowersemiconductor pattern; first to third wire patterns, which arevertically stacked on the second lower semiconductor pattern, and spacedapart from the second lower semiconductor pattern in the thirddirection; and a second gate insulating film, which wraps around thefirst to third wire patterns, and includes a second interface film and asecond high dielectric constant film on the second interface film;wherein from a viewpoint of a cross-sectional area, the first wirepattern includes a first surface extending in the second direction, anda second surface connected to both ends of the first surface and havinga concave curved surface with respect to the second lower pattern;wherein from the viewpoint of the cross-sectional area, the second wirepattern has a first sub-wire pattern in which a width in the seconddirection gradually increases as its distance from the second lowerpattern increases, and a second sub-wire pattern placed on the firstsub-wire pattern in which a width in the second direction graduallydecreases as its distance from the second lower pattern increases, and aheight of the first sub-wire pattern in the third direction is smallerthan a height of the second sub-wire pattern in the third direction; andwherein from the viewpoint of the cross-sectional area, the third wirepattern has an elliptical shape in which a width in the second directionis smaller than a width in the third direction.
 16. The semiconductordevice of claim 15, wherein a width of an upper surface of the firstlower pattern in the second direction is greater than a width of anupper surface of the second lower pattern in the second direction. 17.The semiconductor device of claim 15, wherein a thickness of the firstinterface film is less than a thickness of the second interface film;and wherein a thickness of the first high dielectric constant filmequals a thickness of the second high dielectric constant film.
 18. Thesemiconductor device of claim 15, further comprising: a field insulatingfilm extending on both sides of the second lower semiconductor pattern;wherein the second lower semiconductor pattern includes a first portionwhich overlaps the field insulating film in the second direction, and asecond portion on the first portion; and wherein a slope of a side wallof the second portion of the second lower semiconductor pattern isdifferent from a slope of a side wall of the first portion of the secondlower semiconductor pattern.
 19. The semiconductor device of claim 15,wherein at least two of the first to third sheet patterns have unequalcross-sectional areas.
 20. The semiconductor device of claim 19, whereinat least two of the first to third wire patterns have unequalcross-sectional areas.